In association with development of miniaturization of a field effect transistor, a technique in which a High-k film is used as a gate insulating film instead of a conventional SiO2 film or SiON film has been studied. This technique is for suppressing a gate leakage current which is increased by the tunnel effect and for thinning an equivalent oxide thickness (EOT) to improve a gate capacitance, which result in increase in a driving performance of the field effect transistor.
For example, a specification of U.S. Patent Application Laid-Open Publication No. 2009/0152650 (Patent Document 1) discloses a technique of preventing reoxidation of the gate insulating film, which is made of High-k, by shortening the gate electrode in terms of element separation to be a resolution limit of a lithography technique.
Moreover, C. M. Lai et. al., IEDM Tech. Dig., pp. 655 to 658 (2009)(Non-Patent Document 1) describes a technique of forming a CMOSFET whose gate length is 28 nm by a Gate First process or a Gate Last process.